Field of Invention
The present invention relates to a dual-well metal oxide semiconductor (MOS) device and a manufacturing method thereof; particularly, it relates to such a dual-well MOS device having a reduced conduction resistance and an increased breakdown voltage, and a manufacturing method thereof.
Description of Related Art
FIG. 1 shows a cross-section view of a prior art metal oxide semiconductor (MOS) device 100, which includes: a P-type substrate 101, an epitaxial layer 102, a P-type well 103, an isolation oxide region 104, N-type lightly doped diffusion (LDD) regions 105a and 105b, an N-type source 106, an N-type drain 107, a P-type body region 108, and a gate 111. The isolation oxide region 104 is formed by local oxidation of silicon (LOCOS), to define an operation region 104a which is a major operation region of the MOS device 100. The operation region 104a is indicated by the arrows shown in FIG. 1. The MOS device 100 is an NMOS device, wherein the N-type source 106 connects the N-type LDD region 105a which is at same side of the MOS device 100 as the N-type source 106, and the N-type drain 107 connects the N-type LDD region 105b which is at another side of the MOS device 100 and at same side as the N-type drain 107. The two aforementioned connected regions at two sides of the MOS device 100 are separated by the P-type well 103. Similarly, a prior art PMOS device has the same structure, except that the conductive type of the LDD regions 105a and 105b, the source 106, and the drain 107 are changed to P-type, while the conductive type of the well 103 and the body region 108 are changed to N-type. It is an important trend in the field of semiconductor device to reduce the device size; however, as the channel of the MOS device is shortened, a short channel effect (SCE) caused by drain-induced barrier lowering (DIBL) and hot carrier effect (HCE) will occur. The details of these effects are well-known by one skilled in the art, so they are not redundantly explained here.
As an example, when a gate operation voltage of the MOS device is 5V and the gate length is shorter than 0.6 μm, the SCE starts to occur. To avoid the SCE, the gate length cannot be shorter, unless some solution is proposed to solve this SCE effect. That is, an effective solution is required for an MOS device to be able to operate under certain given operation voltage, and integrated with other devices (or connected in parallel with other MOS devices of the same characteristics) in a circuit, without SCE, while with a reduced size.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a dual-well MOS device having a reduced conduction resistance and an increased breakdown voltage, and a manufacturing method thereof.